1. Field of the Invention
The present invention relates to a reference current circuit and a reference voltage circuit. More particularly, the present invention relates to a bipolar or CMOS reference current circuit formed on a semiconductor integrated circuit, adapted to prevent an appearance of an effect of an early voltage, and operated from a low voltage to output a reference current having a positive temperature characteristic, alternatively to a bipolar or CMOS reference current circuit for outputting a reference current having an optional temperature characteristic. Furthermore, the present invention relates to a bipolar or CMOS reference voltage circuit operated from a low voltage to output a low reference voltage having no temperature characteristics.
2. Description of the Prior Art
First, description will be made of a conventional art regarding a reference current circuit. A reference current circuit has conventionally been available, which is adapted to prevent an appearance of an effect of such an early voltage, and output a reference current having a fixed temperature characteristic. Examples are a bipolar reference current circuit described in Japanese Patent Application Laid-Open No. 191629/1984, and a bipolar reference current circuit and a CMOS reference voltage circuit described in Japanese Patent Application Laid-Open No. 200086/1995.
Now, an operation of the conventional bipolar reference current circuit will be described.
FIG. 1 shows the bipolar reference current circuit described in Japanese Patent Application Laid-Open No. 191629/1984, which is generally called a proportional to absolute temperature (PTAT) current source circuit because it outputs a current proportional to a temperature. However, the PTAT current source circuit shown in FIG. 1 is adapted to prevent an appearance of an effect of an early voltage. It is because collectors of respective transistors Q5 and Q6 are connected to bases of respective transistors Q3 and Q4 and, by setting currents flowing to the transistors Q3 and Q4 equal to each other, base baias voltages of the transistors Q3 and Q4 can be set equal to each other, and thus collector voltages of the transistors Q5 and Q6 are set equal to each other.
In FIG. 1, the transistors Q2 and Q3 are set as unit transistors, and an emitter area ratio of a transistor Q1 is set to be K1 times (K1 greater than 1) as large as that of the unit transistor. Here, if base width modulation is ignored, a relation between a collector current IC of the transistor and a voltage VBE between the base and an emitter is represented by the following equation (1):
IC=KIS exp(VBE/VT)xe2x80x83xe2x80x83(1)
In this case, IS denotes a saturation current of the unit transistor; and VT a thermal voltage, which is represented by VT=kT/q. Here, q denotes a unit electron charge; k Boltzmann constant; T absolute temperature; and K an emitter area ratio with respect to the unit transistor.
Assuming that a DC current amplification factor of the transistor is sufficiently near 1, by ignoring a base current, in the bipolar inverse Widlar current mirror circuit, from the equation (1), relations thus established are represented by the following equations:
VBE1=VT ln{IC1/(K1IS)}xe2x80x83xe2x80x83(2)
VBE2=VT ln(IC2/IS)xe2x80x83xe2x80x83(3)
VBE2=VBE1+R1IC1xe2x80x83xe2x80x83(4)
Now, by solving the equation (4) from the equation (1), a relation of an input/output current of the bipolar inverse Widlar current mirror circuit is obtained by the following equation (5):
IC2=(IC1/K1)exp(R1IC1/VT)xe2x80x83xe2x80x83(5)
FIG. 2 shows an input/output characteristic of the bipolar inverse Widlar current mirror.
In this case, the transistor Q3 drives the transistor Q4. The transistor Q4 constitutes a current mirror circuit having a current mirror ratio of 1:1 with the transistors Q5 and Q6. Since the transistors Q1 and Q2 are respectively driven by the transistors Q5 and Q6, the bipolar self-biased inverse Widlar reference current circuit is provided, and a relation is represented by the following equation (6):
IC2=IC1xe2x80x83xe2x80x83(6)
In the bipolar inverse Widlar current mirror circuit, a mirror current IC2 is exponentially increased with respect to an increase of a reference current IC1. Thus, if an operation point is (Ip=(VT/R1)ln K1=IC1=IC2), then IC1 greater than IC2 is established with Ip greater than IC1, and IC1 less than IC2 is established with Ip less than IC1. Accordingly, when Ip+xcex94I (xcex94I greater than 0) is supplied to the transistors Q4 to Q6, IC4=IC6=IC1=Ip+xcex94I is established. However, since IC2 greater than IC5=Ip+xcex94I is established to cause a shortage of current supplied from the transistor Q5, the base current of the transistor Q3 is pulled, and the transistor Q3 turns off. Thus, a current flowing to the transistor Q3 is reduced, and currents of the transistors Q4 to Q6 are also reduced to return to IP. Conversely, when Ipxe2x88x92xcex94I (xcex94I greater than 0) is supplied to the transistors Q4 to Q6, IC4=IC6=IC1=Ipxe2x88x92xcex94I is established. However, since IC2 less than IC5=Ipxe2x88x92xcex94I is established to cause a current supplied from the transistor Q5 to be excessive, a current is pushed into the base of the transistor Q3, and the transistor Q3 turns on. Accordingly, a current flowing to the transistor Q3 is increased, and currents of the transistors Q4 to Q6 are also increased to return to Ip. That is, a negative feedback current loop is constituted, an operation point is uniquely decided with IC1 greater than 0, realizing a stable operation.
In addition, since the following equation (7) is established,                                                                         Δ                ⁢                                  xe2x80x83                                ⁢                                  V                  BE                                            =                              xe2x80x83                            ⁢                                                                    V                    BE2                                    -                                      V                    BE1                                                  =                                                                            V                      T                                        ⁢                                          ln                      ⁡                                              (                                                                              I                            Cl                                                    /                                                      I                            S                                                                          )                                                                              -                                                            V                      T                                        ⁢                    ln                    ⁢                                          {                                                                        I                          C2                                                /                                                  (                                                                                    K                              1                                                        ⁢                                                          I                              S                                                                                )                                                                                                                                                                                            =                              xe2x80x83                            ⁢                                                                    V                    T                                    ⁢                                      ln                    ⁡                                          (                                                                        I                          Cl                                                /                                                  I                          C2                                                                    )                                                                      =                                                                            V                      T                                        ⁢                                          ln                      ⁡                                              (                                                  K                          1                                                )                                                                              =                                                            R                      1                                        ⁢                                          I                      Cl                                                                                                                              (        7        )            
an equation (8) is obtained:
IC1=IC2=(VT/R1)ln(K1)xe2x80x83xe2x80x83(8)
Here, K1 denotes a constant having no temperature characteristics and, as described above, the thermal voltage VT is represented by VT=kT/q, exhibiting a temperature characteristic of 3333 ppm/xc2x0 C. Accordingly, if a temperature characteristic of a resistor R1 is smaller than that of the thermal voltage VT, exhibiting a primary characteristic with respect to a temperature, an output current I0 of the reference current circuit outputted through the current mirror circuit is proportional to the temperature, realizing a PTAT current source circuit. In this case, since currents flowing to the transistors Q1 to A3 are all equal to one another, base bias voltages of the transistors Q2 and Q3 are also equal to each other. Thus, since collector voltages of the transistors Q5 and Q6 are fixed with these base bias voltages of the transistors Q2 and Q3, and equally set, no effects of Early voltages of the transistors Q1 and Q2 appear. Since no changes occur in a desired current mirror ratio even if the collector voltages of the transistors Q5 and Q6 are changed to cause an appearance of effects of Early voltages, a highly accurate current output having only small changes with respect to fluctuation in a power supply voltage is obtained.
Next, a conventional art regarding a reference voltage circuit will be described. A reference voltage circuit having no temperature characteristics because of cancellation, and adapted to output a reference voltage of 1.2 V or lower has conventionally been available. An example is described in IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp.1790 to 1806, November 1997.
First, an operation of this exemplary reference voltage circuit will be described. FIG. 3 shows the reference voltage circuit described in IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1790 to 1806, November 1997. A current proportional to a temperature is generally outputted. Thus, an output current of a reference current circuit called a proportional to absolute temperature (PTAT) current source circuit is supplied into an output circuit, where it is converted into a voltage and set as a reference voltage.
In FIG. 3, transistors Q1 and Q2 are set as unit transistors, and an emitter area ratio of the transistor Q2 is set to be K1 times (K1 greater than 1) as large as that of the unit transistor. If the base width modulation is ignored, then a relation between a collector current IC of the transistor, and a voltage VBE between the base and an emitter is represented by the following equation (9):
IC=KIS exp(VBE/VT)xe2x80x83xe2x80x83(9)
In this case, IS denotes a saturation current of the unit transistor; and VT the thermal voltage, which is represented by VT=kT/q. Here, q denotes a unit electron charge; k Boltzmann constant; T absolute temperature; and K an emitter area ratio with respect to the unit transistor.
Assuming that a DC current amplification factor of the transistor is sufficiently near 1, if a base current is ignored, relations thus established are represented by the following equations (10) to (12):
VBE1=VT ln(IC1/IS)xe2x80x83xe2x80x83(10)
VBE2=VT ln{IC2/(K1IS)}xe2x80x83xe2x80x83(11)
VBE2=VBE1+R1IC2xe2x80x83xe2x80x83(12)
A solution of the equation (12) from the equation (10) is represented by the following equation (13):
VT ln{K1IC1/IC2}=R1IC2xe2x80x83xe2x80x83(13)
In this case, since a common gate voltage of transistors M4 and M5 are controlled through an operation amplifier to establish the equation (12), the transistors Q1 and Q2 are self-biased, which is represented by the following equation (14).
ID4=ID5=IC1=IC2xe2x80x83xe2x80x83(14)
Accordingly, the equation (13) is obtained by the following equation (15):
ID4=ID5=IC1=IC2=VT ln(K1)/R1xe2x80x83xe2x80x83(15)
In addition, a transistor M6 constitutes a current mirror circuit with the transistors M4 and M5, the following equation (16) is established:
ID4=ID5=ID6xe2x80x83xe2x80x83(16)
A drain current ID6 of the transistor M6 is converted into a voltage by the output circuit, and set as a reference voltage VREF. Assuming that a current flowing to a resistor R2 is xcex3ID6 (0 less than xcex3 less than 1), the reference voltage is represented by the following equation (17):
VREF=VBE3+R2xcex3ID6=R3(1xe2x88x92xcex3)ID6xe2x80x83xe2x80x83(17)
A solution xcex3 of the equation (17) is represented by the following equation (18):
xcex3=(xe2x88x92VBE3+R3ID6)/{ID6(R2+R3)}xe2x80x83xe2x80x83(18)
Accordingly, the reference voltage VREF is obtained by the following equation (19):                                                                         V                REF                            =                              xe2x80x83                            ⁢                                                {                                                            I                      D6                                        ⁡                                          (                                                                        R                          2                                                +                                                  R                          3                                                                    )                                                        }                                ⁢                                  (                                                            V                      BE3                                        +                                                                  R                        2                                            ⁢                                              I                        D6                                                                              )                                                                                                        =                              xe2x80x83                            ⁢                                                {                                                            I                      D6                                        ⁡                                          (                                                                        R                          2                                                +                                                  R                          3                                                                    )                                                        }                                ⁢                                  xe2x80x83                                ⁢                                  {                                                            V                      BE3                                        +                                                                  (                                                                              R                            2                                                    /                                                      R                            1                                                                          )                                            ⁢                                              V                        T                                            ⁢                      ln                      ⁢                                              xe2x80x83                                            ⁢                                              (                                                  K                          1                                                )                                            }                                                                                                                              (        19        )            
In this case, a coefficient term R3/(R2+R3) of the equation (19) is 0 less than R3/(R2+R3) less than 1. Regarding a second term of {VBE3+(R2/R1)VT ln(K1)}, VBE3 has a negative temperature characteristic of about xe2x88x921.9 mV/xc2x0 C., and the thermal voltage VT has a positive temperature characteristic of 0.0853 mV/xc2x0 C. Accordingly, in order to prevent a reference voltage VREF to be outputted from having no temperature characteristics, temperature characteristics are cancelled each other between a voltage having a positive temperature characteristic and a voltage having a negative temperature characteristic. That is, in this case, a value of (R2/R1)ln(K1) is 22.3, and a voltage value of (R2/R1)VT ln(K1) is 0.57 V. Now, if VBE3 is 0.7 V, then {VBE3+(R2/R1)VT ln(K1)}=1.27 V is obtained. Thus, since R3/(R2+R3) less than 1 is established, the reference voltage VREF can be set to a value equal to 1.27 V or lower, e.g., 1.0 V.
However, the following problems are inherent in the conventional reference current circuit.
Conventionally, in the reference current circuit for outputting a reference current having a positive temperature characteristic similar to the above, a non-linear current mirror circuit was used for the PTAT current source circuit, and prevention of an appearance of an effect of an early voltage was achieved only by using the foregoing Widlar current mirror circuit or the Widlar current mirror circuit described in the other embodiment of Japanese Patent Application Laid-Open No. 191629/1984 as the non-linear current mirror circuit.
In addition, it is difficult to provide a reference current circuit having an optional temperature characteristic, adapted to prevent an appearance of an effect of an early voltage, by a currently available technology.
Reference current circuits are usually used for bias currents in circuits of an LSI including an analog LSI, a digital LSI such as a memory, and many other kinds of an LSI. Especially, the reference current circuit for outputting a current proportional to a temperature is generally called a PTAT current source circuit. However, higher integration of an LSI has made a process more detailed, lowering a power supply voltage. At present, therefore, other than the reference current circuit having a positive temperature characteristic, a reference current circuit having an optional temperature characteristic is requested. For example, a reference voltage circuit can be easily realized by converting an output current of a reference current circuit having no temperature characteristics into a voltage through a resistor, and an output voltage of an optional value can be obtained. The reference voltage circuit having no temperature characteristics is generally called a band gap reference voltage circuit, and its output voltage is near a band gap voltage 1.205 V of silicon (Si) at absolute zero. Thus, a normal operation is no longer possible by a nominal output voltage 1.2 V of a nickel-hydrogen battery or a nickel-cadmium battery as a currently most general secondary battery.
Next, problems inherent in the conventional reference voltage circuit will be described. Conventionally, in the reference voltage circuit for outputting a reference voltage having no temperature characteristics, since an operation amplifier was used for a feedback circuit of the PTAT current source circuit, operation was difficult by a low power supply voltage. That is, reference voltage circuits are usually used for bias currents in circuits of an LSI including an analog LSI, a digital LSI such as memory devices, and many other kinds of an LSI. Especially, the reference voltage circuit for outputting a voltage having no temperature characteristics is generally called a band gap reference voltage circuit. Its output voltage is near a band gap voltage 1.205 V of silicon (Si) at absolute zero.
However, higher integration of an LSI has made a process more detailed, lowering a power supply voltage. At present, therefore, a normal operation is no longer possible by a low nominal output voltage of about 1.2 V of a nickel-hydrogen battery or a nickel-cadmium battery as a current most general battery.
An object of the present invention is to provide a reference current circuit operated from a low power supply voltage of about 1 V, and adapted to output a current having a positive or optional temperature characteristic. Specifically, the object of the present invention is to provide a PTAT current source circuit using the Nagata current mirror circuit, and adapted to prevent an appearance of an effect of an early voltage, and a reference current circuit having an optional temperature characteristic by using the PTAT current source circuit thus obtained.
Another object of the present invention is to provide a reference voltage circuit operated from a low power supply voltage of about 0.9 V, and adapted to output a voltage having no temperature characteristics by simple and small circuitry.
In accordance with a first aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a first node, and the other end connected to a second node, a first transistor connected between the second node and the ground line, and having a control terminal connected to the first node, and a second transistor connected between a third node and the ground line, and having a control terminal connected to the second node, and the third transistor has a control terminal connected to the third node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
In accordance with a second aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a second node, and the other end connected to the ground line, a first transistor connected between the first and second nodes, and having a control terminal connected to the first node, and a third node, and a second transistor connected between a fourth node and the ground line, and having a control terminal connected to the third node, and the third transistor has a control terminal connected to the third node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
In accordance with a third aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a fourth node, and the other end connected to the ground line, a first transistor connected between a first node and the ground line, and having a control terminal connected to each of the first node and a second node, and a second transistor connected between a third node and the fourth node, and having a control terminal connected to the second node, and the third transistor has a control terminal connected to the third node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
In accordance with a fourth aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line; and second and third resistors. In this case, the current mirror circuit includes a first resistor having one end connected to a second node, and the other end connected to the ground line, a first transistor connected between the first and second nodes, and having a control terminal connected to the first node and a third node, and a second transistor connected between a fourth node and the ground line, and having a control terminal connected to the third node, the second resistor has one end connected to the first node, and the other end connected to the ground line, the third resistor has one end connected to the fourth node, and the other end connected to the ground line, and the third transistor has a control terminal connected to the fourth node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
In accordance with a fifth aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line; and second and third resistors. In this case, the current mirror circuit includes a first resistor having one end connected to a first node, and the other end connected to a second node, a first transistor connected between the second node and the ground line, and having a control terminal connected to the first node and a third node, and a second transistor connected between the third node and the ground line, and having a control terminal connected to the second node, the second resistor has one end connected to the first node, and the other end connected to the ground line, the third resistor has one end connected to the third node, and the other end connected to the ground line, and the third transistor has a control terminal connected to the third node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
In accordance with a sixth aspect of the present invention, there is provided a reference current circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; a third transistor connected between the power supply line and the ground line; and second and third resistors. In this case, the current mirror circuit includes a first resistor having one end connected to a fourth node, and the other end connected to a second node, a first transistor connected between a first node and the ground line, and having a control terminal connected to the first and second nodes, and a second transistor connected between a third node and the fourth node, and having a control terminal connected to the second node, the second resistor has one end connected to the first node, and the other end connected to the ground line, the third resistor has one end connected to the third node, and the other end connected to the ground line, and the third transistor has a control terminal connected to the third node, drives the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop.
Furthermore, the reference current circuit of the present invention may employ various suitable application forms described below.
A current outputted from the reference current circuit is supplied into a fifth resistor. The fifth resistor includes a plurality of resistors connected in series.
In addition, according to the reference current circuit of the present invention, a current of the third transistor is set to be substantially inversely proportional to a temperature, a current mirror circuit current flowing to the transistor of the current mirror circuit and the current of the third transistor are weighted and added, and an output current having a fixed temperature characteristic is obtained.
In accordance with a seventh aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a second node, and the other end connected to the ground line, a first transistor connected between a first node and the second node, and having a control terminal connected to the first node and a third node, and a second transistor connected between a fourth node and the ground line, and having a control terminal connected to the third node,
the reference voltage circuit being self-biased to constitute a reference current circuit, and including a second resistor having one end connected to a fourth node, and the other end connected to a fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current of the reference current circuit to paths of the third transistor and the third resistor through the second resistor.
In accordance with an eighth aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a first node, and the other end connected to a second node, a first transistor connected between the second node and the ground line, and having a control terminal connected to the first node, and a second transistor connected between a third node and the ground line, and having a control terminal connected to the second node,
the reference voltage circuit being self-biased to constitute a reference current circuit, and including a second resistor having one end connected to a fourth node, and the other end connected to a fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current of the reference current circuit to paths of the third transistor and the third resistor through the second resistor.
In accordance with a ninth aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a fourth node, and the other end connected to the ground line, a first transistor connected between a first node and the second node, and having a control terminal connected to the first node and a second node, and a second transistor connected between a third node and the fourth node, and having a control terminal connected to the second node,
the reference voltage circuit being self-biased to constitute a reference current circuit, and including a second resistor having one end connected to the fourth node, and the other end connected to a fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current of the reference current circuit to paths of the third transistor and the third resistor through the second resistor.
In accordance with a tenth aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a second node, and the other end connected to the ground line, a first transistor connected between a first node and the second node, and having a control terminal connected to the first node and a third node, and a second transistor connected between a fourth node and the ground line, and having a control terminal connected to the third node,
the third transistor connected between a fifth node and the ground line drives a reference transistor of the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop, and
the reference voltage circuit including a second resistor having one end connected to the fourth node, and the other end connected to the fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current proportional to a current of the current source for driving the first and second transistors to paths of the third transistor and the third resistor through the second resistor.
In accordance with an eleventh aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a first node, and the other end connected to a second node, a first transistor connected between the second node and the ground line, and having a control terminal connected to the first node, and a second transistor connected between a third node and the ground line, and having a control terminal connected to the second node, and
the third transistor connected between a fifth node and the ground line wire drives a reference transistor of the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop,
the reference voltage circuit including a second resistor having one end connected to a fourth node, and the other end connected to the fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current proportional to a current of the current source for driving the first and second transistors to paths of the third transistor and the third resistor through the second resistor.
In accordance with a twelfth aspect of the present invention, there is provided a reference voltage circuit, comprising: a power supply line; a ground line; a current mirror circuit installed between the power supply line and the ground line; and a third transistor connected between the power supply line and the ground line. In this case, the current mirror circuit includes a first resistor having one end connected to a fourth node, and the other end connected to the ground line, a first transistor connected between a first node and the ground line, and having a control terminal connected to the first node and a second node, and a second transistor connected between a third node and the fourth node, and having a control terminal connected to the second node, and
the third transistor connected between a fifth node and the ground line drives a reference transistor of the current mirror circuit for setting a current source for driving the first and second transistors as a mirror current, and constitutes a negative feedback current loop,
the reference voltage circuit including a second resistor having one end connected to the fourth node, and the other end connected to the fifth node, the third transistor connected between the fifth node and the ground line, and having a control terminal connected to the fifth node, and a third resistor having one end connected to the fourth node, and the other end connected to the ground line, and an output voltage being obtained by supplying an output current proportional to a current of the current source for driving the first and second transistors to paths of the third transistor and the third resistor through the second resistor.
The reference voltage circuit of the present invention may employ various suitable application forms described below.
That is, an output circuit composed of a fourth transistor having a control terminal connected through the second resistor to a current input terminal, and a current output terminal connected to the ground line, and the third resistor having one terminal connected to the ground line, and the current mirror circuit for driving the output circuit are series-connected by n stages, and n output voltages are outputted.
According to the reference voltage circuit of the present invention, an output circuit composed of a fourth transistor having a control terminal connected through the second resistor to a current input terminal, and a current output terminal connected to the ground line, and the third resistor having one terminal connected to the ground line is series-connected by n stages, and n output voltages are outputted by sharing a circuit current.
According to the reference current circuit of the present invention, the first to third transistors are bipolar transistors.
According to the reference current circuit of the present invention, the first to third transistors are field-effect transistors.
According to the reference voltage circuit of the present invention, the first to third transistors are bipolar transistors.
Furthermore, according to the reference voltage circuit of the present invention, the first to third transistors are field-effect transistors.
According to the reference current circuit of the present invention, in the non-linear current mirror circuit composed of the two transistors having different voltages between bases and emitters (or between gates and sources), self-biasing sets a collector (or drain) current of each to be a current IPTAT proportional, or substantially proportional to a temperature. On the other hand, the voltage between the base and the emitter (or between the gate and the source) has a negative temperature characteristic. Thus, a current proportional to the voltage between the base and the emitter (or between the gate and the source) is set to be a current IIPTAT substantially inversely proportional to the temperature.
Therefore, by weighting and adding the current IPTAT flowing to the transistor of the non-linear current mirror circuit, and the current IIPTAT proportional to the current between the base and the emitter (or between the gate and the source), an output current IREF(=IPTAT+IIPTAT) having a fixed temperature characteristic is obtained. Moreover, by converting the output current IREF into a voltage, a reference voltage circuit for outputting an optional voltage value having a fixed temperature characteristic can be provided.
However, in the conventional reference voltage circuit, by weighting and adding a voltage VPTAT proportional to an absolute temperature, and a voltage VIPTAT inversely proportional to the absolute temperature, a reference voltage circuit having a fixed temperature characteristic is provided. Thus, in the conventional reference voltage circuit, an operation power supply voltage exceeding VPTAT+VIPTAT(=1.2 V), e.g., 1.4 V or higher, was necessary. According to the present invention, however, a stable operation is provided even by a lower power supply voltage.